I suspect you are drawing incorrect conclusions.
Maybe one device is faster but CL of 15 or CL of 17 is the CAS latency in
clock cycles, which needs to be divided by the bus speed in hertz to get the cache latency in seconds (usually reported in nano seconds). When a CL 15 device runs on a bus speed of 1066.67 MHz and a CL 17 device runs on 1200 Mhz (which is supposed to be the
standard specification) then the CAS latency is 14.063 ns and 14.16 ns respectively. A difference of 0.69%.
The experiment compares a device with a lower data rate and a higher latency with a device with a higher data rate and a lower latency, or that would appear to be the case. I don't know if it's the case or not, but possibly the DDR4 2133 was actually running at the same bus speed as the DDR4 2400. Usually RAM and mother boards have documentation for recommended settings, that would mean the DDR4 2133 15-15-15-35 was basically a DDR4 2400 15-15-15-35 and the CAS latency would be 12.5 ns. These RAM devices use an external clock and usually there are more than one recommended setting.
I'd expect (maybe as a first hypothesis) that comparison of the wall time for a fully memory bound computation that doesn't take advantage of prefetching (or can't benefit) to have a close correspondence to the difference in clock latency measured in nano seconds. If the computation takes advantage of prefetching (from memory into CPU cache) I'd expect a correspondence to the difference in memory transfer rate. One possibility is that the behavior is more indicative of the program used to control KataGo, I think I remember that Sabaki is a Python program and I usually use Katrain, another Python program, and observe that it occasionally uses a lot of memory and CPU and GPU resources (that is the Graphical Processing Unit not the Go Processing Unit).
The DDR5 devices quoted (far) above are different in that one has both a higher data rate and a lower latency than the other, it's should be better all around. The only issue is the possibility the cost of upgrading memory later.
By the way the
official AMD website states that the CPU (same CPU or?) supports 4 DIMMs for DDR5-3600 or less and 2 DIMMs for DDR5-5200 or less. With this information I'd assume that the 4x DDR5-4200 or 2x DDR5-5600 would operate as DDR5-3600 or DDR5-5200, since the memory controller is, I believe, built into the AMD CPUs. Then again AMD does somewhat encourage overclocking, it's supposed to void the warranty though.
===Edit for some reason I wrote cache latency but it's called call CAS latency (column address strobe latency).